Circuit and method for driving a load, in particular a high-intensity discharge lamp, and a control unit for said circuit

ABSTRACT

Circuit for driving a load, comprising: two input terminals for connection to a source of a supply voltage; a first and a second output terminal for connection to the load; at least one inductor coupled between one of the output terminals and a corresponding connection node; at least one arrangement comprising a switch coupled between one of said input terminals and one of said connection nodes, a diode being connected between said one connection node and the other input terminal; a control unit for controlling said one or more switches; wherein each arrangement and corresponding diode are designed to allow the voltage over the opened switch of said arrangement to return to substantially zero before said switch is closed, the control unit being designed to provide a signal for closing the switch when a substantially zero voltage over said opened switch is detected. Turning the switch on at a substantially zero voltage means that switching losses are greatly reduced, and this without complicating the circuit.

The present invention relates to a circuit for driving a load,comprising:

-   -   two input terminals for connection to a source of a supply        voltage;    -   a first and a second output terminal for connection to the load;    -   at least one inductor coupled between one of the output        terminals and a corresponding connection node;    -   at least one arrangement comprising a switch coupled between one        of said input terminals and one of said connection nodes, a        diode being connected between said one connection node and the        other input terminal;    -   a control unit for controlling said at least one switch.

Such a circuit is for example known from U.S. Pat. No. 6,384,544. Thisdocument discloses a ballast for high-intensity discharge lamps, whereinthe steady-state running current of the lamp may be controlled usingonly two power switches. The circuit is provided with current limitingmeans which measure the current through the lamp, and disable thecurrent by opening the active switch when it is too high. When thecurrent decreases, the active switch is turned on again. This feed-backmechanism turns the active switch on independently of the voltage overthe switch at that time, causing switching losses to occur.

The general object of the invention is to provide a circuit for drivinga load, typically a high-intensity discharge lamp, with a limited numberof components and low switching losses.

This object is achieved by designing each arrangement and correspondingdiode to allow the voltage over the switch of said each arrangement toreturn to substantially zero before said switch is closed, the controlunit being designed to provide a signal for closing the switch when asubstantially zero voltage is detected over said opened switch.

Turning the switch on at a substantially zero voltage means thatswitching losses are greatly reduced, and this without complicating thecircuit. A control unit can be used to obtain this criticaldiscontinuous current mode, which is the most efficient mode for drivinga load such as a high-intensity discharge lamp.

When high-intensity discharge (HID) lamps, for instance a metal halidelamp, are operated during the steady-state operation, it is beneficialto deliver a well-defined power level to the lamp independently of thelamp voltage, and without having too many losses, such as switchinglosses, etc.

As HID lamps are susceptible to acoustic resonance at high frequencies,HID lamps are preferably driven at relatively low frequencies (typically100 Hz) with a square wave current.

A preferred embodiment of the circuit of the invention for driving aload with a substantially square wave current comprises:

-   -   a first arrangement comprising a first switch coupled between        the first input terminal and one of the said connection nodes, a        diode being connected between said one connection node and the        second input terminal;    -   a second arrangement comprising the second switch coupled        between the second input terminal and one of the said connection        nodes, a diode being connected between said one connection node        and the first input terminal;    -   the control unit being designed to generate its control signals        in commutation intervals, said first switch being operated        during a first interval causing a load current having        substantially a first direction, and said second switch being        operated during a second interval causing a load current having        substantially the opposite direction.

During a first commutation interval the first switch is operated. When afirst switch is conducting, an increasing current will flow from thefirst input terminal via the switch through the inductor. The currentcontinues to increase until a determined condition is fulfilled (forinstance when a peak current is reached), at which moment the switch isopened. At that moment the capacitor which models the internalcapacitance of the switch seen in the connection node, takes over theinductor current, causing the capacitor voltage to decrease rapidlyuntil the diode is switched on. The diode now takes over the inductorcurrent. The inductor current decreases further and crosses zero. Thediode stops conducting and the capacitor takes over the current in thereverse direction, causing the capacitor voltage to rise rapidly. Whenthe voltage over the capacitor reaches the voltage of the first inputterminal, the switch can be turned on again. In the case of anarrangement comprising only a MOSFET switch, the internal body diode ofthe switch M1 will conduct during a very short period just beforeturning the switch back on. In this way switching-on takes place whenthe voltage drop over the switch is substantially zero, so that thelosses are minimal.

This zero voltage switching of the first switch is repeated until thereoccurs a commutation moment. At such a moment the first commutationinterval ends, and the second commutation interval starts. During thesecond commutation interval the second switch is repeatedly switched onand off while the first switch is kept in its non-conducting state. Itwill be apparent that the same phases can be distinguished and that thecurrent flows in the opposite direction through the lamp circuit.

The used switches are preferably MOSFET devices. IGBTs could be used aswell, but have the drawback that the current losses are too high whenthey are switched off. MOSFETs switch off very rapidly and are thereforepreferred.

According to a first embodiment of the circuit of the invention, a firstinductor is coupled between an output terminal and a first connectionnode, and a second inductor is coupled between said output terminal anda second connection node, wherein the first switch is coupled betweensaid first connection node and the first input terminal and the secondswitch are coupled between said second connection node and the secondinput terminal.

This embodiment with two independent down-stages is especiallyadvantageous because the number of components is limited and because thecircuit does not require any shottky diodes. Because the circuit can beoperated by the control unit in the transition mode, the losses areminimal.

According to a second embodiment of the circuit of the invention, eacharrangement comprises a series connection of the switch with two diodescoupled in anti-parallel, which first and second arrangement are coupledbetween the respective input terminals and a common connection nodeconnected to one side of the inductor.

This is a variant with one down-stage which can be operated undersubstantially the same conditions as the already described embodiments.

According to a further aspect of the invention the control unit isdesigned to generate a commutation control signal for controlling thecommutation intervals and a switching signal having a higher frequencythan said commutation control signal for controlling the operation ofthe active switch, wherein said commutation and said switching signalare synchronized by the control unit.

This synchronization ensures a well-defined commutation moment andavoids unexpected current or voltage behavior in the circuit.

According to a first variant of the invention the commutation controlsignal ensures a commutation from said first interval to said secondinterval when the current through the one or more inductors issubstantially zero.

Apart from the switching losses during the first interval when the firstswitch is operated, and during the second interval when the secondswitch is operated, commutation losses when switching from the first tothe second interval can also be taken into account, although they areusually less important. However the commutating switching losses canalso be minimized by synchronizing the high-frequency switching actionwith the low-frequency switching action, wherein the roles of theswitches can be interchanged during zero current.

According to a second variant the commutation control signal ensures acommutation from said first interval to said second interval when thecurrent through the at least one inductor is substantially maximum.

In the second embodiment of the invention, which will be furtherdescribed in FIG. 9, the commutation at maximum current, correspondswith a substantially zero voltage over the switch which is going tobecome active, and can also be advantageous.

The invention further relates to a method for driving a load, comprisingthe steps of:

-   -   turning on a switch for providing current through an inductor to        the load;    -   turning off said switch when the current through the inductor        reaches a determined value.

The method of the invention is distinguished in that, after turn-off ofthe switch, the current is directed so that it continues to flow untilthe voltage over the switch is substantially zero, at which time theswitch is turned on again.

In this way switching losses are greatly reduced.

The invention also relates to a control unit for use in any of the abovedescribed embodiments of the circuit or the method of the invention,wherein said control unit comprises:

-   -   two capacitors coupled in series between one input terminal and        one of the connection nodes, wherein the divider node between        the two capacitors is coupled via a resistor to a logic circuit;    -   said logic circuit being designed to provide a signal which        turns on the corresponding switch connected to said connection        node when the voltage in the divider node falls within a        predetermined voltage range.

Such a control unit can be used in the circuit or the method of theinvention so as to ensure that closing of the switch takes place at asubstantially zero voltage over this switch.

According to a first variant, the logic circuit further comprises atimer which starts running when the active switch is turned on until apre-set time period has elapsed and the logic circuit provides a signalfor turning off the switch.

According to another variant, the logic circuit further comprises meansfor detecting a peak current in the load (4), wherein the logic circuitprovides a signal for turning off the switch (M1;M2) when said peakcurrent is detected.

These and other aspects of the present invention will become apparentfrom and be elucidated with reference to the illustrative embodimentsdescribed hereinafter by way of non-limiting indication, and on thebasis of the attached drawings, in which:

FIG. 1 is a schematic circuit block diagram of a prior art ballast;

FIG. 2 is schematic circuit diagram of a first embodiment of acommutating-forward driver circuit according to the invention;

FIG. 3 represents schematically the current and/or voltage waveforms atvarious points of the circuit of FIG. 2;

FIG. 4 shows a preferred embodiment of the control unit for use with thecircuit of FIG. 2 according to the invention;

FIG. 5 shows signals at various points of the control circuit of FIG. 4during operation of the circuit;

FIG. 6 is a waveform diagram showing the current through the lamp I_(L)and the voltage over the lamp V_(L), when the circuits of FIGS. 2 and 4are used;

FIG. 7 shows a detail view of the voltage and current waveforms of FIG.6 during commutation;

FIG. 8 is a waveform diagram showing the lamp circuit current I_(LC)being the sum of the currents through the respective inductors L1 andL2, when the circuits of FIG. 2 and 4 are used;

FIG. 9 shows a second embodiment of a commutating-forward driver circuitaccording to the invention;

FIG. 10 shows signals at various points of the control circuit of FIG. 4when said control circuit is used to control the second embodiment shownin FIG. 9, and when it is connected as described.

FIG. 1 shows a ballast circuit which is suitable for both igniting andoperating an HID lamp 4. A first circuitry block 1, typically comprisinga rectifier and an up-converter, converts an AC input voltage into ahigh DC output voltage, typically in the order of 500 V. This high DCvoltage is provided between two output terminals 9, 10 of block 1 andused as the supply voltage for respectively the igniter circuit 2 andthe forward commutating stage 3 fulfilling the function of adown-converter and a commutator into one integrated stage.

The igniter circuit 2 causes a current peak in the primary winding 7 inorder to generate a high voltage peak at the secondary winding 6.

The commutating-forward stage 3 provides a square wave current tooperate the lamp during the run-up phase of the lamp and in steadystate.

The following discussion concerns commutating-forward stages using ahalf-bridge configuration, but a person skilled in the art willunderstand that the explanation below can also be applied to acommutating-forward stage 3 using a full-bridge configuration.

FIG. 2 shows a commutating-forward driver 3 according to a firstembodiment of the invention, which can be used to perform the method ofthe invention. The driver has two input terminals 11, 12 for connectionto the output terminals 9, 10 of the first block 1.

A first MOSFET switch M1 has its drain and source terminals connected torespectively the first input terminal 11 and connection node 15. A firstfast recovery diode D1 is connected between connection node 15 and inputterminal 12, so that it forms a series connection to the first MOSFETM1. A second MOSFET switch M2 has its source and drain terminalsconnected to respectively the second input terminal 12 and connectionnode 16. A second fast recovery diode D2 is connected between connectionnode 16 and the first input terminal 11, so that it forms a seriesconnection to the second MOSFET M2.

The respective connection nodes 15, 16 are connected to separateinductors 28 and 29, which are both connected to a first output terminal26. One side of the lamp 4 is connected to the output terminal 26. Afilter capacitor 18 is placed in parallel with the lamp 4. Thetransformer 6, 7 and said capacitor 18 serve to smoothen the currentthrough the lamp 4.

The driver 3 further comprises a control unit 20 having at least twooutput terminals 21, 22 which are connected to the respective gates ofthe two MOSFETs M1, and M2. The control unit 20 is designed to open andclose the MOSFET switches M1, M2 by supplying the gate of these deviceswith a control signal S1, S2. The control unit 20 typically comprises anarrangement for detecting the voltage between connection nodes 15, 16and the input terminal 12, a logic circuit 20′ and a level shiftercircuit 59. When the detection arrangement detects a substantially zerovoltage over the active opened switch (M1 or M2), a signal for closingthe corresponding switch is produced via the logic circuit 20′ and thelevel shifter circuit 59. The level shifter 59 has the main task ofraising the “1” output of the logic circuit 20′ to a suitable voltage toswitch on M1 or M2.

The detection arrangement comprises a first capacitive divider 42, 43coupled between one input terminal 12 and the first connection node 15,wherein the divider node 82 between the two capacitors 42, 43 is coupledvia a resistor 78 to a logic circuit 20. This first divider is used todetermine when the voltage over the first switch is substantially zero.The detection arrangement further comprises a second arrangement 40, 41for determining when the voltage over the second switch is substantiallyzero.

The logic circuit 20′ is designed to provide a signal which turns on thecorresponding switch when the voltage in the divider node falls within apredetermined voltage range.

Suitable values for the various components of the driver circuitdesigned for driving an HID lamp, typically a metal halide lamp, are asfollows: M1 en M2, 7B60C, inductor 28, 29, 300 :H, diode D1 and D2,MUR160, capacitor 40, 42, 33 pF, capacitor 41, 43, 330 pF.

It will be appreciated that the values given above for the variouscomponents of the circuit are merely illustrative, and that other valuesand designs are also suitable based on the particular criteria andpreferences of the circuit designer.

The typical behavior of this commutating-forward driver circuit will nowbe described with reference to the voltage and current waveforms shownin FIG. 3.

A signal S1, S2 causing a corresponding switch to close will beindicated in FIG. 3 as a logical value “1”, whereas a signal S1, S2causing a corresponding switch to open will be indicated as a logical“0”. The sum of the current through the respective inductors 28 and 29will be referred to as the lamp circuit current I_(LC), while thecurrent through the lamp is referred to as I_(L).

During a first commutation interval 30, five main operational phases canbe distinguished, these being indicated in FIG. 2 with the arrows A1-A5.When the signal S1 is such that MOSFET M1 is conducting, i.e. S1=“1”, anincreasing current will flow from input terminal 11 via MOSFET M1through inductor L1, as indicated with the arrow A1. The currentcontinues to increase until a peak current Ip is reached and M1 isswitched off by setting signal S1 to “0”. At that moment the parallelcapacitor 19, which models the internal capacitance as seen in node 15,takes over the inductor current as indicated with arrow A2, causing thecapacitor voltage to decrease rapidly until the diode D1 is switched on.Diode D1 now takes over the inductor current as shown with arrow A3. Theinductor current I_(LC) decreases further and crosses zero. Diode D1stops conducting and the parallel capacitor 19 takes over the current inthe reverse direction, causing the capacitor voltage to rise rapidly.When the voltage over the parallel capacitor 19 reaches the voltage ofthe first input terminal 11, the internal body diode 23 of the MOSFET M1will conduct during a very short period, as shown by arrow A5, and T1can be switched on again by applying a signal S1=“1”. In this wayturning on the switch takes place when the voltage drop over the MOSFETM1 is substantially zero or, in other words, a zero-voltage switchinghas been performed according to the method of the present invention.Phase 1 will now start again.

This zero-voltage switching of the first MOSFET M1 is repeated until acommutation moment. At such a moment the first commutation interval 30ends, and the second commutation interval 31 starts. During the secondcommutation interval 31 the second MOSFET M2 is repeatedly switched onand off, while the first MOSFET M1 is held in its non-conducting state.It will be apparent that the same five phases can be distinguished andthat the current flows in the opposite direction through the lampcircuit.

FIG. 4 illustrates the logic circuit 20′ of a control unit 20 accordingto the invention. The capacitive dividers 40, 41 and 42, 43 areconnected to the input pins 82 and 83 of the logic circuit 20′. Thesevoltage levels are transferred to logic Voltage levels via two Schmitttriggers 48, 49. One trigger output 67 corresponding with the voltage inconnection node 16 is inverted with inverter 50, so that this output ishigh when a zero voltage is detected. On the assumption that the circuitis operated in the second commutation interval, and hence switch M1 ispermanently open (thus output 68 is low), the output 69 of the XOR 51switches from low to high when a zero voltage is detected. This causes arising edge at the entrance of the master flip-flop 52, so that theoutput Q of the master flip-flop 52 is high, and hence the output pin 61of the driver 58 is high as well. This output pin is connected to alevel shifter circuit 59 for switching on the switch which is beingoperated, which is determined by output pin 60 of the logic circuit 20′.

For the sake of clarity the truth table of the flip-flops 52, 55 and 56is given below:

Inputs Outputs CD SD D CLK Q Not Q L H X X L H Clear H L X X H L PresetL L X X L L H L L L−>H L H H H H L−>H H L H H X H−>L Qn Not Qn

The low frequency signal, typically a 100 Hz square wave signal, isprovided at input pin 63. This signal is synchronized with thehigh-frequency signal at the output of flip-flop 52 by means of twosubsequent flip-flops 55 and 56.

This synchronized signal is used to determine the commutation time ofthe driver circuit of the lamp.

Flip-flop 55 is coupled with the output “not Q” of the master flip-flop52 to trigger the flip-flop 55 on a master reset. The Q output offlip-flop 55 is connected with a latch 57 for providing an output signalin output pin 62.

Output pin 62 is connected via a first diode 92 with input pin 82, andvia a second diode 93 with input pin 83. These diodes 92, 93 ensure thatinput pin 82 is maintained high when switch M1 is active (firstcommutation interval), and that input pin 83 is maintained low whenswitch M2 is active (second commutation interval).

The turn-on time of the switches can be determined by differentconditions. The logic circuit comprises a timer 54 which starts runningafter a zero-voltage detection (switch is turned on), which timer 54 hasan output which becomes high when a pre-set time T has elapsed. Thiscauses a low value (via the NOR element 53) at the CD pin of theflip-flop 52, which brings the output Q of said flip-flop 52 to lowstate and turns off the switch. Other inputs can be coupled to the NORelement 53 in order to turn off the switch. For example, a signal whichrises when a peak current or an over-voltage is detected.

FIG. 5 shows the signals at various points of the logic circuit 20′, andfurther illustrates the above explained behavior of the control unit 20.Note that the commutation moment is synchronized with the control signalin node 61 (V61) for the active switch, and that commutation occurs whenthe current (I_(CL)) is substantially zero.

FIG. 6 shows the current through the lamp I_(L) and the voltage over thelamp V_(L), when the circuits of FIGS. 2 and 4 are used. The power ofthe lamp was 73 Watt. The scale of the y-axis is respectively 50 V/majordivision for V_(L), and 1 A/major division for I_(L), while time isshown along the X-axis in 500 :s/major division.

FIG. 7 shows a detail view of the voltage and current waveforms of FIG.6 during commutation. The scale of the y-axis is respectively 50 V/majordivision for V_(L), and 1 A/major division for I_(L), while time isshown along the X-axis in 10 :s/major division. The commutation time islargely determined by the values of the capacitors and inductors used inthe circuit.

FIG. 8 is a waveform diagram showing the lamp circuit current I_(LC)being the sum of the currents through the respective inductors 28 and29, when the circuits of FIGS. 2 and 4 are used, and for a lamp power of73 Watt. The scale of the y-axis is 1 A/major division for I_(LC), whiletime is shown along the X-axis in 10 :s/major division The current peaksjust after commutation are typically detected by peak current detectionmeans (not shown in FIGS. 2 and 4) providing the NOR element 53 with ahigh input, and hence clearing the master flip-flop 52, in order toswitch off the active switch.

FIG. 9 represents a second embodiment of the circuit according to theinvention. In this circuit a first arrangement 80 coupled between inputterminal 11 and connection node 15 comprises a series connection of aswitch M1 with two diodes coupled in anti-parallel 70,71. A secondsimilar arrangement 81 is coupled between the input terminals 12 and thecommon connection node 15 connected to one side of a single inductor 28.The operating principles are similar to those described above and willnot be repeated here.

The logic circuit 20′ described in FIG. 4 can also be used to controlthe circuit of FIG. 9. The connections are different however; output pin60 is not used, whereas output pin 62 now provides the synchronizedcommutation signals. Furthermore only one capacitive divider is used andoutput pin 62 is not connected via diodes to the input pins 82, 83, butis connected to the level shifter and to the input pin 82 of the logiccircuit 20′. In this way a different synchronization is obtained duringcommutation, as can be seen in FIG. 10. Here, the role of the MOSFETswitches M1, M2 is changed when the current through the inductor 28 ismaximum. Note however that the voltage over the switch which is going tobecome active is substantially zero at that time.

The invention is not limited by the above illustrated preferredembodiments, many modifications of which can be envisaged. The scope andspirit of the invention is set forth in the following claims.

1. A circuit for driving a load, comprising: two input terminals forconnection to a source of a supply voltage; a first output terminal anda second output terminal for connection to the load; at least oneinductor coupled between one of the output terminals and a correspondingconnection node; at least one arrangement comprising a switch coupledbetween one of said input terminals and one of said connection nodes, adiode being connected between said one connection node and the otherinput terminal; a control unit for controlling said switch; wherein saidat least one arrangement and a corresponding diode are designed to allowthe voltage over an opened switch of said at least one arrangement toreturn to substantially zero before said opened switch is closed, thecontrol unit being designed to provide a signal for closing the openedswitch when a substantially zero voltage over said opened switch isdetected.
 2. The circuit according to claim 1, wherein said switches areMOSFET switches.
 3. A circuit for driving a load with a substantiallysquare wave current, comprising: a first input terminal and a secondinput for connection to a source of a supply voltage; a first outputterminal and a second output terminal for connection to the load; atleast one inductor coupled between one of the first output terminal andthe second output terminal and a corresponding connection node; a firstarrangement comprising a first switch coupled between the first inputterminal a first connection node, and a first diode connected betweensaid first connection node and the second input terminal; a secondarrangement comprising a second switch coupled between the second inputterminal and a second connection node, and a second diode connectedbetween said second connection node and the first input terminal; and acontrol unit for controlling said first switch and said second switch;wherein said first arrangement and said second arrangement are designedto allow a voltage over an opened switch of said first arrangement andsaid second arrangement to return to substantially zero before saidopened switch is closed, the control unit being designed to provide asignal for closing the opened switch when a substantially zero voltageover said opened switch is detected; and wherein the control unit isfurther designed to generate control signals in commutation intervals,said first switch being operated during a first interval causing a loadcurrent having substantially a first direction, and said second switchbeing operated during a second interval causing a load current havingsubstantially a second direction which is opposite the first direction.4. The circuit according to claim 3, wherein a first inductor is coupledbetween said first output terminal and said first connection node, and asecond inductor is coupled between said first output terminal and saidsecond connection node, and wherein the first switch is coupled betweensaid first connection node and the first input terminal and the secondswitch is coupled between said second connection node and the secondinput terminal.
 5. The circuit according to claim 3, wherein the firstarrangement and the second arrangement each comprises a seriesconnection of a switch with two diodes coupled in anti-parallel, andwherein the first arrangement and the second arrangement are coupledbetween respective input terminals and a common connection nodeconnected to one side of the inductor.
 6. The circuit according to claim3, wherein the control unit is further designed to generate acommutation control signal for controlling the commutation intervals anda switching signal having a higher frequency than said commutationcontrol signal for controlling operation of an active switch, whereinsaid commutation and said switching signal are synchronized by thecontrol unit.
 7. The circuit according to claim 6, wherein thecommutation control signal ensures a commutation from said firstinterval to said second interval when a current through the at least oneinductor is substantially zero.
 8. The circuit according to claim 6,wherein the commutation control signal ensures a commutation from saidfirst interval to said second interval when a current through the atleast one inductor is substantially maximum.
 9. A control unit for usein a circuit for driving a load, the circuit comprising: two inputterminals for connection to a source of a supply voltage; a first outputterminal and a second output terminal for connection to the load; atleast one inductor coupled between one of the output terminals and acorresponding connection node; at least one arrangement comprising aswitch coupled between one of said input terminals and one of saidconnection nodes, a diode being connected between said one connectionnode and the other input terminal; a control unit for controlling saidswitch; wherein said at least one arrangement and a corresponding diodeare designed to allow the voltage over an opened switch of said at leastone arrangement to return to substantially zero before said openedswitch is closed, the control unit being designed to provide a signalfor closing the opened switch when a substantially zero voltage oversaid opened switch is detected; wherein said control unit comprises: twocapacitors coupled in series between one input terminal and one of theconnection nodes, wherein a divider node between the two capacitors iscoupled via a resistor to a logic circuit; said logic circuit beingdesigned to provide a signal which turns on the switch when a voltage inthe divider node falls within a predetermined voltage range.
 10. Thecontrol unit according to claim 9, wherein said logic circuit furthercomprises a timer which starts running when the active switch is turnedon until a pre-set time period has elapsed, wherein the logic circuitprovides a signal for turning off the switch when this pre-set timeperiod has elapsed.
 11. unit according to claim 9, wherein said logiccircuit further comprises means for detecting a peak current in theload, wherein the logic circuit provides a signal for turning off theswitch when said peak current is detected.